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Central processing unit
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81	Designing and Building Applications for Extreme Scale Systems CS598 William Gropp www.cs.illinois.edu/~wgropp Add to Reading List Source URL: wgropp.cs.illinois.edu Language: English - Date: 2015-01-14 21:48:04 Parallel computing Free software Numerical linear algebra Bill Gropp MPICH Portable Extensible Toolkit for Scientific Computation Educational technology Central processing unit Message Passing Interface
82	Adaptive Line Placement with the Set Balancing Cache Dyer Rolán Basilio B. Fraguela Ramón Doallo Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2009-09-04 07:55:51 Cache Computer architecture Computer memory Central processing unit CPU cache Cache algorithms Memory hierarchy Lookup table Saturation arithmetic Draft:Cache memory
83	Godson-2E software manual Contents 1 Godson-2E Micro Architecture...................................................................................1 1.1 Godson Series Processors ........................................ Add to Reading List Source URL: dev.lemote.com Language: English - Date: 2011-05-04 12:04:52 Central processing unit CPU cache Translation lookaside buffer Loongson Processor register Control register Instruction set Addressing mode MIPS instruction set Draft:Cache memory
84	Using Cortex-M3 and Cortex-M4 Fault Exception Application Note 209 Abstract The Cortex-M processors implement an efficient exception model that also traps illegal memory accesses and several incorrect program conditions. Add to Reading List Source URL: www.keil.com Language: English - Date: 2016-03-11 03:37:29 Computer errors Memory management Central processing unit Instruction set architectures ARM architecture Bus error Control register Page fault Segmentation fault Memory protection ARM Cortex-M Exception handling
85	Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Er Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2015-08-21 02:18:29 Central processing unit Microprocessors Computer architecture Parallel computing Instruction set architectures Multi-core processor ARM architecture Microarchitecture ARM Cortex-A15 AMD 10h ARM big.LITTLE Processor register
86	Optimization of Sparse Matrix-Vector Multiplication on Emerging Multicore Platforms Samuel Williams∗†, Leonid Oliker∗, Richard Vuduc§, John Shalf∗, Katherine Yelick∗†, James Demmel† ∗ CRD/NERSC, Lawrenc Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-07 00:12:17 Computer memory Cache Computer architecture Compiler optimizations CPU cache Central processing unit Opteron Cell Sparse matrix-vector multiplication Loop nest optimization Multi-core processor Advanced Micro Devices
87	Chapter 4 CPU Design Reading: The corresponding chapter in the 2nd edition is Chapter 5, in the 3rd edition it is Chapter 5 and in the 4th edition it is Chapter Add to Reading List Source URL: eceweb.ucsd.edu Language: English - Date: 2015-07-31 19:30:10 Instruction set architectures Central processing unit Instruction set Sign extension Datapath Classic RISC pipeline DLX
88	1 Optimal Tile Size Selection Guided by Analytical Models∗ Basilio B. Fraguelaa , Mart´ın G. Carmuejaa , Diego Andradea a Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2005-09-23 06:13:05 Cache Computer architecture Computer memory Central processing unit CPU cache Optimizing compiler Memory hierarchy Genetic algorithm Program optimization Algorithm Itanium Cache-oblivious algorithm
89	IBM T. J. Watson Research Center Evaluation of Blue Gene/Q HTM Joint work with Amy Wang, Matthew Gaudet, Peng Wu, Martin Ohmacht, Jose Amaral, Christopher Barton, Raul Silvera Add to Reading List Source URL: rp-www.cs.usyd.edu.au Language: English Computer memory Cache Computer architecture CPU cache Central processing unit Parallel computing Blue Gene Speculative
90	Keeping the PilGRIM at a steady pace Avoiding pipeline stalls in a lazy functional processor Arjan Boeijink University of Twente Enschede Add to Reading List Source URL: staff.fnwi.uva.nl Language: English - Date: 2014-01-16 12:00:20 Central processing unit Stack Instruction set Heap Models of computation Stack machines Assembly languages

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